The present invention relates to digital systems. More particularly, the present invention relates to initialization of digital logic circuits having a memory characteristic.
A digital system, such as a digital application specific integrated circuit (ASIC), typically includes both combinational logic circuits and memory elements. A combinational logic circuit, which is made up of combinations of logic gates, has no memory characteristic and thus its output depends only on the current value of its inputs. Flip-flops are typical memory elements used for sequential logic such as registers, counters, and finite state machines (FSM). When such a digital system is powered up, or needs to be reset, all the flip-flops need to be initialized so as place the system to a known initialized (or default) state.
A reset signal, often referred to as a system reset signal or global reset signal, is typically employed to initialize the digital system. A reset signal may be automatically generated when an ASIC or a device containing the ASIC is powered up. A reset signal may also be generated when the digital system needs to be re-initialized, for example, when the system is rebooted, or when the system starts communicating with another system. The reset signal can be applied to flip-flops either synchronously or asynchronously. In an asynchronous reset, a reset signal is applied to an asynchronous port, typically a reset (RST) port or preset (SET) port, of each flip-flop of the system. The initialization is not in synchronism with a clock signal for the system. On the other hand, in a synchronous reset, a reset signal is applied to a synchronous control port of each flip-flop, and the flip-flops of the system are initialized in synchronism with the system""s clock signal.
In an embedded system, such as a system-on-a-chip architecture, various processors or circuit cores are integrated on a single chip, and there are many clock domains. For example, as shown in FIG. 1A, a first circuit core 10 and a second circuit core 12 may be in different clock domains 14 and 16, respectively. Also, as shown in FIG. 1B, a circuit core 18 may have a plurality of clock domains 20 and 22. When circuitry in one clock domain is initialized by a reset signal from outside of the clock domain, a clock signal necessary for synchronous initialization of that clock domain may not be readily available. For example, as shown in FIG. 1A, when the first circuit core 10 is initialized by the second circuit core 12, a reset signal is sent from the second circuit core 12 and a clock signal for the first circuit core 10 is also activated. Such a clock signal for the first clock domain 14 may be generated within the first circuit core 10 or supplied as a peripheral or external clock signal. However, when the first circuit core 10 is in the initialization phase after receiving the reset signal, the clock signal may not have started toggling so as to properly trigger the initialization.
Accordingly, since a synchronous reset may not properly initialize circuitry in one clock domain, asynchronous initialization has been employed in a conventional digital system. That is, all memory elements such as flip-flops of the circuit core 10, or in the same clock domain of the core 18, are reset asynchronously in a conventional system. FIG. 2 schematically illustrates such a conventional digital system 30 employing an asynchronous reset scheme. As shown in FIG. 2, the digital system 30 is in a first clock domain 31 (with clock signal Clock 1). A reset signal (Reset) and a data signal (Data) which typically follows the reset signal are provided from a second clock domain 32 (with clock signal Clock 2). The reset signal is supplied to all of the time-sensitive digital logic circuits 34 (34a-34c) in the first clock domain 31. The digital logic circuits 34 are typically asynchronous-reset flip-flops.
FIG. 3 schematically illustrates signal waveforms in the conventional asynchronous initialization. As shown in FIG. 3, the reset signal Reset (waveform 40) is activated at time t1 and then deactivated at time t2. The time period from time t1 to time t2 is an initialization sequence, and may have a specific number of cycles of the clock signal Clock 2 (waveform 42). However, the clock signal Clock 1 (waveform 44) for a synchronized operation is not available until time t3 after the initialization sequence has already past. Thus, it is necessary that a timing-sensitive digital logic circuit (such as a flop-flop) is asynchronously initialized in response to activation of the reset signal Reset at time t1. The output (Q) of the flip-flop (waveform 46) has an invalid value until time t1 when the flip-flop is initialized. Then, when the clock signal Clock 1 becomes active at time t3, the flip-flop begins outputting a valid functional value.
In order to asynchronously reset a digital logic circuit, it needs to have an asynchronous port. However, for example, an asynchronous-reset flip-flops with an asynchronous port is larger than a synchronous-reset flip-flop. Also, an asynchronous reset signal has to be connected to a number of asynchronous flip-flops in the system. The large-sized asynchronous-reset flip-flops and a reset signal bus with many fanouts require a larger area of the chip. In addition, a large number of fanouts add the loading on the reset signal. Under heavy loading, the pulse of the reset signal may set the flip-flops closer to the source, but it would be so attenuated by a long bus wiring that it is invisible to other fanouts far away from the source. Alternatively, if the active clock signal should be provided at the-time when the reset signal is active, additional logic is required, increasing the cost and die area.
Accordingly, it would be desirable to provide a method and system for synchronously initializing a digital circuit system with a minimal number of asynchronous-reset flip-flops, so as to save the die area and reduce loading on the reset signal.
A method and digital system synchronously initialize a logic circuit having a memory characteristic. The digital system is in a first clock domain. The digital system includes a first logic circuit and a second logic circuit. The first logic circuit includes an asynchronous port for receiving a reset signal from a second clock domain, a port for receiving a first clock signal for the first clock domain, and an output port for providing an initialization signal. The first logic circuit sets the initialization signal at a first logic value in response to the reset signal and maintains the first logic value at least until the first clock signal becomes active. The second logic circuit includes a synchronous port for receiving the initialization signal, a port for receiving the first clock signal, and a data output port outputting a data signal. The second logic circuit is initialized in response to the active first clock signal when the initialization signal has the first logic value. The method includes (a) receiving a reset signal from a second clock domain, (b) activating the initialization signal in response to the reset signal, (c) maintaining the initialization signal active at least until the first clock signal becomes active, (d) initializing the digital logic circuit in response to the first clock signal when the first clock signal becomes active, and (e) deactivating the initialization signal in response to the active first clock signal.